Loading debug/FCC_Sys_New_simulink_design_verifier_execution_20200625_203409.txt→debug/issue_1_open.txt +0 −0 File moved. View file debug/issue_2_open.txt 0 → 100644 +34 −0 Original line number Diff line number Diff line 25-Jun-2020 21:31:21 Preprocessing model...done Checking compatibility for property proving: model 'ActuatorLoop_Verify' Compiling model...done Building model representation...done 25-Jun-2020 21:31:36 'ActuatorLoop_Verify_replacement' is compatible for property proving with Simulink Design Verifier. Proving properties using model representation from 25-Jun-2020 21:31:36... Running additional analysis to reduce instances of rational approximation... UNDECIDED DUE TO NONLINEARITIES Verification Subsystem/Proof Objective1 Objective: T Analysis Time = 00:00:28 25-Jun-2020 21:33:42 Property proving was stopped. Generating output files: 25-Jun-2020 21:33:46 Results generation completed. Data file: D:\Documents\SCHOOL\McSCert\do178\sldv_output\ActuatorLoop_Verify\ActuatorLoop_Verify_sldvdata.mat Loading
debug/FCC_Sys_New_simulink_design_verifier_execution_20200625_203409.txt→debug/issue_1_open.txt +0 −0 File moved. View file
debug/issue_2_open.txt 0 → 100644 +34 −0 Original line number Diff line number Diff line 25-Jun-2020 21:31:21 Preprocessing model...done Checking compatibility for property proving: model 'ActuatorLoop_Verify' Compiling model...done Building model representation...done 25-Jun-2020 21:31:36 'ActuatorLoop_Verify_replacement' is compatible for property proving with Simulink Design Verifier. Proving properties using model representation from 25-Jun-2020 21:31:36... Running additional analysis to reduce instances of rational approximation... UNDECIDED DUE TO NONLINEARITIES Verification Subsystem/Proof Objective1 Objective: T Analysis Time = 00:00:28 25-Jun-2020 21:33:42 Property proving was stopped. Generating output files: 25-Jun-2020 21:33:46 Results generation completed. Data file: D:\Documents\SCHOOL\McSCert\do178\sldv_output\ActuatorLoop_Verify\ActuatorLoop_Verify_sldvdata.mat