Commit 28ac0497 authored by Stephen Scott's avatar Stephen Scott
Browse files

Added updated outer loop verification

parent 5dcf0ae2

src/verification/sldv_output/Heli_inner_loop_Verify/Heli_inner_loop_Verify_replacement.mdl

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src/verification/sldv_output/Heli_inner_loop_Verify/sldv_log_2020_7_16_13_26_29.txt

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16-Jul-2020 13:26:02

Preprocessing model...done

Checking compatibility for property proving: model 'Heli_inner_loop_Verify'

Compiling model...done

Building model representation...done



16-Jul-2020 13:26:06

'Heli_inner_loop_Verify_replacement' is compatible for property proving with Simulink Design Verifier.





Proving properties using model representation from 16-Jul-2020 13:26:06...



FALSIFIED

Verification Subsystem/Proof Objective1

Objective: Point([T T T])

Analysis Time = 00:00:22





16-Jul-2020 13:26:29



Completed normally.



Generating output files:



16-Jul-2020 13:26:29

Results generation completed.



    Data file:

    D:\Documents\SCHOOL\McSCert\do178\src\verification\sldv_output\Heli_inner_loop_Verify\Heli_inner_loop_Verify_sldvdata.mat